ai
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P61 PARALLEL COUNTERS
ai, aldec, altera, amd, apple, arm, artificial-intelligence, careers, clock, digital, formalverification, fpga, fpgadesign, freshersjobs, functionalverification, hdl, infineon, intel, inteljobs, jobinvlsi, jobs, learnverilog, machine-learning, python, qualcomm, quartus, questasim, rtl, rtldesign, semicon, semiconductor, semiconductorjobs, simulation, synopsis, systemdesign, systemverilog, technology, testbench, uvm, verification, verilog, verilogdesign, veriloglife, verilogmaster, verilogskilss, vhdl, vivado, vlsi, vlsidesign, vlsifreshers, vlsijobs, vlsiopenings, vlsisystem, vlsitools, vlsitraining, xilinxMultiple-input circuits that count the number of their inputs that are in a given state (normally logic ONE) are called PARALLEL COUNTERS. (from IEEE TRANSACTIONS ON COMPUTERS, VOL. C-22, NO. 11, NOVEMBER 1973). OR Counting the number of ones in vectors while processing on single input is also a PARALLEL COUNTERS. Applications of parallel counters…
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P55 CONSTRAINTS-1
ai, aldec, altera, amd, apple, arm, business, careers, clock, computers, digital, formalverification, fpga, fpgadesign, freshersjobs, functionalverification, hdl, infineon, intel, inteljobs, jobinvlsi, jobs, learnverilog, qualcomm, quartus, questasim, rtl, rtldesign, semicon, semiconductor, semiconductorjobs, simulation, sql, synopsis, systemdesign, systemverilog, technology, testbench, uvm, verification, verilog, verilogdesign, veriloglife, verilogmaster, verilogskilss, vhdl, vivado, vlsi, vlsidesign, vlsifreshers, vlsijobs, vlsiopenings, vlsisystem, vlsitools, vlsitraining, xilinxThis post is about constraint in system verilog. They are used when you want to restrict your input within some values or within some ranges. As an example, Let say you have designed 3 bit half adder and while verifying you always want to give one input as 0 and other input you want to…
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P46 SPATIAL CONVOLUTION
ai, aldec, altera, amd, apple, arm, artificial-intelligence, careers, clock, data-science, deep-learning, digital, formalverification, fpga, fpgadesign, freshersjobs, functionalverification, hdl, infineon, intel, inteljobs, jobinvlsi, jobs, learnverilog, machine-learning, qualcomm, quartus, questasim, rtl, rtldesign, semicon, semiconductor, semiconductorjobs, simulation, synopsis, systemdesign, systemverilog, testbench, uvm, verification, verilog, verilogdesign, veriloglife, verilogmaster, verilogskilss, vhdl, vivado, vlsi, vlsidesign, vlsifreshers, vlsijobs, vlsiopenings, vlsisystem, vlsitools, vlsitraining, xilinxLet say I have P1=(a1,b1,c1) & P2=(a2,b2,c2) and I am trying to find outP = dot product of P1 and P2 = P1.P2 if a1,b1,c1,a2,b2,c2 all are 4 bit each Why am I interested in dot product ? The answer will take us to the most talked areas which before few years was not so…
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P41 GENERIC KNOWLEDGE-2
ai, aldec, altera, amd, apple, arm, career, careers, clock, digital, formalverification, fpga, fpgadesign, freshersjobs, functionalverification, hdl, infineon, intel, inteljobs, jobinvlsi, jobs, learnverilog, linear-algebra, machine-learning, math, mathematics, qualcomm, quartus, questasim, rtl, rtldesign, semicon, semiconductor, semiconductorjobs, simulation, synopsis, systemdesign, systemverilog, testbench, uvm, verification, verilog, verilogdesign, veriloglife, verilogmaster, verilogskilss, vhdl, vivado, vlsi, vlsidesign, vlsifreshers, vlsijobs, vlsiopenings, vlsisystem, vlsitools, vlsitraining, xilinxMy MATHS teacher used to say , “Learn and Understand MATRIX otherwise “you will play computer games, but you will not be able to design one. “ And the irony today is, “the GAME(reinforcement learning) itself is redefining the matrix operations.” Yes, I am talking about the DeepMind’s published paper (October 2022) in NATURE that…
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While designing RTL, may times you will come across like these specs, So, For Sure, You need to use the counter here. But you need to use the counter sensibly in these types of scenario. One such case is here where I am queueing next module via led when my count is greater or equals…
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Generally when we write Finite State Machine in Verilog, We got three options for assigning the value to the states. They are For 4 states FSM, we will see, what value we assign in all encoding methods. In this post I will only talk about One Hot Encoding. One-hot is faster and it suits high-speed…
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Ternary Operator The post goes on Latches and Ternary Operator ( Conditional Operator ). so, for this example, what do you think, How many latches will be generated ? so, the answer goes like this. Now, Latch will come into picture only if loop is not closed. as in This will create one latch because…
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Linear Feedback Shift Register INTERVIEWER : WRITE DOWN A CODE FOR SYNTHESIZABLE AND NON-REPETITIVE “VERILOG” CODE for generating RANDOM NUMBERS. Let’s build on this first. Let say you are generating two bit random numbers. and you want it without repetition. as an example for two bit numbers it will go as “0,2,1,3”,”0,2,1,3″,”0,2,1,3″. so what you…