Multiple-input circuits that count the number of their inputs that are in a given state (normally logic ONE) are called PARALLEL COUNTERS. (from IEEE TRANSACTIONS ON COMPUTERS, VOL. C-22, NO. 11, NOVEMBER 1973).

OR

Counting the number of ones in vectors while processing on single input is also a PARALLEL COUNTERS.

Applications of parallel counters are so wide starting from communications to content addressable memory.

Let’s try to look into HAMMING WEIGHT COUNTER i.e. counting number of ones in a given vectors.

Now there are multiple ways.

I have shown 4 ways here. Surprisingly (or not surprisingly 🙂 ) synthesized ckt of all are same.

module hamming_weight 
(
input  [3:0] a_in,
output [2:0] b_out
); 

wire [3:0] a_d,b_d ; 

assign a_d[3:2]  = { a_in[3] & a_in[2] , a_in[3] ^ a_in[2] };
assign a_d[1:0]  = { a_in[1] & a_in[0] , a_in[1] ^ a_in[0] };

assign b_d[3:2]  = { a_d[3] & a_d[2] , a_d[3] ^ a_d[2] };
assign b_d[1:0]  = { a_d[2] & a_d[1] , a_d[2] ^ a_d[1] };

assign b_out[2]  = b_d[3];
assign b_out[1]  = b_d[2] ^ b_d[1];
assign b_out[0]  = b_d[0] ;

endmodule 

module hamming_weight 
(
input  [3:0] a_in,
output [2:0] b_out
); 

integer i = 0;
reg [2:0] a = 'b0;

always@*
begin 
a = 'b0;
for(i=0;i<4;i=i+1)
begin 
  if(a_in[i])
   a = a + 1'b1;
  end 
end
assign b_out = a;
endmodule 

module hamming_weight 
(
input  [3:0] a_in,
output [2:0] b_out
); 

integer i = 0;

always@*
begin 
b_out = 'b0;
for(i=0;i<4;i=i+1)
begin 
  if(a_in[i])
   b_out = b_out + a_in[i];
  end 
end 
endmodule 

module hamming_weight 
(
input  [3:0] a_in,
output [2:0] b_out
); 

always@*
begin   
 case(a_in)
 4'b0000                                         : b_out = 3'b0   ; 
 4'b0001,4'b0010,4'b0100,4'b1000                 : b_out = 3'b1   ;
 4'b1001,4'b1010,4'b1100,4'b0101,4'b0110,4'b0011 : b_out = 3'b10  ; 
 4'b1011,4'b1110,4'b0111,4'b1101                 : b_out = 3'b11  ; 
 4'b1111                                         : b_out = 3'b100 ;
  endcase
end   

endmodule 

but but but, as an RTL ENGINEER you should always look into the parameter “SCALABILITY“.

As you keep on increasing the width of the vectors, resources and delays will increase more and more.

In that case, only the module in left top is the better one.

Can you write the generalized equation for that one ?

Hint : It is built using Half Adder.

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• P69 RAM/ROM
• P68 BACK TO BASICS-3
• P67 BACK TO BASICS-2
• P66 BACK TO BASICS-1
• P65 IF-ELSE_IF-ELSE SYNTHESIZER

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