February 2024
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Sensitivity List – 2 (In continuation with previous post P11) Inside Sensitivity list only Two event operators are allowed w.r.t synthesis and both are of same meaning. so, always@(a,b,c) is same as always@(a or b or c). REMEMBER “or” keyword is only allowed inside sensitivity list w.r.t synthesizable code. that means if you use “and”,…
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P11 SYNTAX RULES-1
aldec, altera, amd, apple, arm, careers, clock, digital, formalverification, fpga, fpgadesign, freshersjobs, functionalverification, hdl, infineon, intel, inteljobs, jobinvlsi, jobs, learnverilog, qualcomm, quartus, questasim, rtl, rtldesign, semicon, semiconductor, semiconductorjobs, simulation, synopsis, systemdesign, systemverilog, testbench, uvm, verification, verilog, verilogdesign, veriloglife, verilogmaster, verilogskilss, vhdl, vivado, vlsi, vlsidesign, vlsifreshers, vlsijobs, vlsiopenings, vlsisystem, vlsitools, vlsitraining, xilinxSensitivity List I am going write the syntax rules pertaining to sensitivity list. So, Can you answer about a,b,c,d,e…. if it is allowed or not ? ANSWERS : #vlsi #vlsitraining #systemverilog #verilog #verification #semiconductor #digital #vhdl #verilogmaster #vlsidesign #verilogdesign #hdl #fpgadesign #jobinvlsi #fpga #functionalverification #formalverification #rtl #systemdesign #rtldesign #xilinx #vivado #questasim #vlsiopenings #verilogskilss #freshersjobs #vlsifreshers…
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P10 SEQUENTIAL VS COMBINATIONAL-1
aldec, altera, amd, apple, arm, careers, clock, digital, formalverification, fpga, fpgadesign, freshersjobs, functionalverification, hdl, infineon, intel, inteljobs, jobinvlsi, jobs, learnverilog, qualcomm, quartus, questasim, rtl, rtldesign, semicon, semiconductor, semiconductorjobs, simulation, synopsis, systemdesign, systemverilog, testbench, uvm, verification, verilog, verilogdesign, veriloglife, verilogmaster, verilogskilss, vhdl, vivado, vlsi, vlsidesign, vlsifreshers, vlsijobs, vlsiopenings, vlsisystem, vlsitools, vlsitraining, xilinxWhat decides synthesized ckt to be sequential or combinational ? In the beginning of my career I used to think that how the synthesizer tools is deciding that my coded circuit is SEQUENTIAL or COMBINATIONAL? How the tool is so intelligent ? ANSWER is very simple. In the sensitivity list, if you don’t see anything…
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P9 CASE-4
aldec, altera, amd, apple, arm, careers, clock, digital, formalverification, fpga, fpgadesign, freshersjobs, functionalverification, hdl, infineon, intel, inteljobs, jobinvlsi, jobs, learnverilog, qualcomm, quartus, questasim, rtl, rtldesign, semicon, semiconductor, semiconductorjobs, simulation, synopsis, systemdesign, systemverilog, testbench, uvm, verification, verilog, verilogdesign, veriloglife, verilogmaster, verilogskilss, vhdl, vivado, vlsi, vlsidesign, vlsifreshers, vlsijobs, vlsiopenings, vlsisystem, vlsitools, vlsitraining, xilinxThe post is in continuation with the last post. Yes, It infers two latches because when sel1 = 00, o1 is provided input a but o2 is not given anything.So, it has to remember the last value, for the same it uses the latch.Again for when sel1 = 10, o1 will give one latch. So,…
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P8 CASE-3
aldec, altera, amd, apple, arm, careers, clock, digital, formalverification, fpga, fpgadesign, freshersjobs, functionalverification, hdl, infineon, intel, inteljobs, jobinvlsi, jobs, learnverilog, qualcomm, quartus, questasim, rtl, rtldesign, semicon, semiconductor, semiconductorjobs, simulation, synopsis, systemdesign, systemverilog, testbench, uvm, verification, verilog, verilogdesign, veriloglife, verilogmaster, verilogskilss, vhdl, vivado, vlsi, vlsidesign, vlsifreshers, vlsijobs, vlsiopenings, vlsisystem, vlsitools, vlsitraining, xilinxTry to ANSWER THIS. I got two questions for you regarding this post. #vlsi #vlsitraining #systemverilog #verilog #verification #semiconductor #digital #vhdl #verilogmaster #vlsidesign #verilogdesign #hdl #fpgadesign #jobinvlsi #fpga #functionalverification #formalverification #rtl #systemdesign #rtldesign #xilinx #vivado #questasim #vlsiopenings #verilogskilss #freshersjobs #vlsifreshers #vlsijobs #testbench #vlsisystem #semiconductorjobs #uvm #intel #vlsitools #qualcomm #arm #learnverilog #altera #quartus #amd #infineon #apple…
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P7 CASE CONUNDRUM-2
aldec, altera, amd, apple, arm, careers, clock, digital, formalverification, fpga, fpgadesign, freshersjobs, functionalverification, hdl, infineon, intel, inteljobs, jobinvlsi, jobs, learnverilog, mux, mux-to, networknewswire-release, qualcomm, quartus, questasim, rtl, rtldesign, semicon, semiconductor, semiconductorjobs, simulation, synopsis, systemdesign, systemverilog, testbench, uvm, verification, verilog, verilogdesign, veriloglife, verilogmaster, verilogskilss, vhdl, vivado, vlsi, vlsidesign, vlsifreshers, vlsijobs, vlsiopenings, vlsisystem, vlsitools, vlsitraining, xilinxSo, There are 3 ways to avoid the latch in the case. All 3 ways are depicted here. ONE MORE THING, If you observe, Elaborated ckt uses MUXES and SYNTHESIZED ckt uses LUTs. There are no GATES here, Only MUXES are there. and that is the reason why interviewer asks to design the ckt with…
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P6 CASE CONUNDRUM-1
aldec, altera, amd, apple, arm, careers, clock, digital, formalverification, fpga, fpgadesign, freshersjobs, functionalverification, hdl, infineon, intel, inteljobs, jobinvlsi, jobs, learnverilog, qualcomm, quartus, questasim, rtl, rtldesign, semicon, semiconductor, semiconductorjobs, simulation, synopsis, systemdesign, systemverilog, testbench, uvm, verification, verilog, verilogdesign, veriloglife, verilogmaster, verilogskilss, vhdl, vivado, vlsi, vlsidesign, vlsifreshers, vlsijobs, vlsiopenings, vlsisystem, vlsitools, vlsitraining, xilinxCASE & LATCH This post is about one of the favorite question of RTL Interviewer.Q: In What Case , the “case” gives latch ? Look at the snippet. Now in the code , we are designing a MUX. Based on the selection line input (sel1/sel2) one of the input (a,b,c,d) gets assigned to output o1/o2.…
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P5 SIMULATION SYNTHESIS MISMATCH-1
aldec, altera, amd, apple, arm, careers, clock, digital, formalverification, fpga, fpgadesign, freshersjobs, functionalverification, hdl, infineon, intel, inteljobs, jobinvlsi, jobs, learnverilog, qualcomm, quartus, questasim, rtl, rtldesign, semicon, semiconductor, semiconductorjobs, simulation, synopsis, systemdesign, systemverilog, testbench, uvm, verification, verilog, verilogdesign, veriloglife, verilogmaster, verilogskilss, vhdl, vivado, vlsi, vlsidesign, vlsifreshers, vlsijobs, vlsiopenings, vlsisystem, vlsitools, vlsitraining, xilinxAnswer of both of these question I am going to explain in this post through this snippet. For COMBINATIONAL circuit, synthesizer tool will take into consideration of all the signal those are there in the right side in the procedural block (a,b,c in the code ) and it also considers which are there in the…
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P4 TERNARY OPERATOR-1
aldec, altera, amd, apple, arm, careers, clock, digital, formalverification, fpga, fpgadesign, freshersjobs, functionalverification, hdl, infineon, intel, inteljobs, jobinvlsi, jobs, learnverilog, qualcomm, quartus, questasim, rtl, rtldesign, semicon, semiconductor, semiconductorjobs, simulation, synopsis, systemdesign, systemverilog, testbench, uvm, verification, verilog, verilogdesign, veriloglife, verilogmaster, verilogskilss, vhdl, vivado, vlsi, vlsidesign, vlsifreshers, vlsijobs, vlsiopenings, vlsisystem, vlsitools, vlsitraining, xilinxOne of the most commonly asked question in the ⓇⓉⓁ Interview is If you are using 𝗧𝗘𝗥𝗡𝗔𝗥𝗬 operator and if you are using single 𝗶𝗳 𝗮𝗻𝗱 𝗲𝗹𝘀𝗲, What is the difference between them ? ANSWER : Both of them are same after synthesis and in simulation. Check the image above, where both o1 and o2…
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This post is in continuation with the last post. This post is just to show an example that your synthesized netlist will depend on the tool/library. Last post I have used Vivado as the synthesis Tool which has the option to choose from FDRE,FDPE,FDCE etc. which are FF design in the Xilinx FPGAs based on…