P42 RESOURCE REDUCTION

Apr 26, 2024

aldec, altera, amd, apple, arm, careers, clock, digital, formalverification, fpga, fpgadesign, freshersjobs, functionalverification, hdl, infineon, intel, inteljobs, jobinvlsi, jobs, learnverilog, qualcomm, quartus, questasim, reset, rtl, rtldesign, semicon, semiconductor, semiconductorjobs, simulation, synopsis, systemdesign, systemverilog, testbench, uvm, verification, verilog, verilogdesign, veriloglife, verilogmaster, verilogskilss, vhdl, vivado, vlsi, vlsidesign, vlsifreshers, vlsijobs, vlsiopenings, vlsisystem, vlsitools, vlsitraining, xilinx

If the synthesis library is having active low synchronous reset FF and you keep same reset in your design, your design will work at optimum speed.

nonetheless if your strict requirement is to use active high reset, the synthesizer will put up extra NOT gate. that’s all.

It may or may not affect the design speed.

so, Generally designers keep reset (sync/async/active low/active high ) based on the requirement.

always@(posedge clk) 
if(!rst) 
  a <= 1'b0;
else  
  a <= b;

So, the code is for synchronous active low flip-flop.

Now this library is having implici active high reset.

As in fig as I have used active low reset, then the synthesizer has put one NOT gate. (1-LUT).

#vlsi #vlsitraining #systemverilog #verilog #verification #semiconductor #digital #vhdl #verilogmaster #vlsidesign #verilogdesign #hdl #fpgadesign #jobinvlsi #fpga #functionalverification #formalverification #rtl #systemdesign #rtldesign #xilinx #vivado #questasim #vlsiopenings #verilogskilss #freshersjobs #vlsifreshers #vlsijobs #testbench #vlsisystem #semiconductorjobs #uvm #intel #vlsitools #qualcomm #arm #learnverilog #altera #quartus #amd #infineon #apple #veriloglife #synopsis #aldec #semicon #jobs #simulation #clock #inteljobs #careers

Discover more from Verilog Master

Subscribe to get the latest posts to your email.

P42 RESOURCE REDUCTION

Share this:

Discover more from Verilog Master

Leave a comment Cancel reply