verilogdesign
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P30 LATCH CONUNDRUM-2
aldec, altera, amd, apple, arm, careers, clock, digital, formalverification, fpga, fpgadesign, freshersjobs, functionalverification, hdl, infineon, intel, inteljobs, jobinvlsi, jobs, learnverilog, qualcomm, quartus, questasim, rtl, rtldesign, semicon, semiconductor, semiconductorjobs, simulation, synopsis, systemdesign, systemverilog, testbench, uvm, verification, verilog, verilogdesign, veriloglife, verilogmaster, verilogskilss, vhdl, vivado, vlsi, vlsidesign, vlsifreshers, vlsijobs, vlsiopenings, vlsisystem, vlsitools, vlsitraining, xilinxTernary Operator The post goes on Latches and Ternary Operator ( Conditional Operator ). so, for this example, what do you think, How many latches will be generated ? so, the answer goes like this. Now, Latch will come into picture only if loop is not closed. as in This will create one latch because…
Verilog Master 