Ternary Operator

The post goes on Latches and Ternary Operator ( Conditional Operator ).

module latch_conun_2 
(
  input  [2:0] d1,d2,d3,
  output [3:0] wid
);
  assign wid = (d1<=2) ? 14 :(d2<=3) ? 8 :(d3<=4) ? 6 : 2;
endmodule 

so, for this example, what do you think, How many latches will be generated ?

Go back

Your message has been sent

Choose several options
Warning


so, the answer goes like this.

Now, Latch will come into picture only if loop is not closed. as in

if(i)
  begin
    a = 1'b1;
  end

This will create one latch because it is given as store a = 1 when i = 1 but we did not tell what to do when i = 0. so, for i=0, it will hold the last value of a.

but if you see ternary operator, TERNARY OPERATOR itself is a closed loop.

so, two things we need to remember w.r.t. Ternary Operator

  1. When using ternary operator with assign, it will never create latch.
  2. When using inside procedural block, it will create the latch only when feedback is given. i.e. always@(*) a = res ? 1'b1 : a; otherwise without feedback, it will never create latch.

so, it you see in 2nd, a is output and a also use in input. so, feedback is given. In this case latch will be generated.

so, for the above question, as the ternary operator is used with the assign, there will not be any latch generated.




Discover more from Verilog Master

Subscribe to get the latest posts sent to your email.

Leave a comment